Achieving programming model abstractions for reconfigurable computing

Authors:
David Andrews;Ron Sass;Erik Anderson;Jason Agron;Wesley Peck;Jim Stevens;Fabrice Baijot;Ed Komp
Affiliations:
Electrical Engineering and Computer Science Department, University of Kansas, Lawrence, KS;Department of Electrical and Computer Engineering, University of North Carolina, Charlotte, NC;Information Science Institute, University of Southern California, Los Angeles, SC;Information and Telecommunication Technology Center, University of Kansas, Lawrence, KS;Information and Telecommunication Technology Center, University of Kansas, Lawrence, KS;Information and Telecommunication Technology Center, University of Kansas, Lawrence, KS;Information and Telecommunication Technology Center, University of Kansas, Lawrence, KS;Information and Telecommunication Technology Center, University of Kansas, Lawrence, KS
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

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Abstract

This paper introduces hthreads, a unifying programming model for specifying application threads running within a hybrid computer processing unit (CPU)/field-programmable gate-array (FPGA) system. Presently accepted hybrid CPU/FPGA computational models--and access to these computational models via high level languages--focus on programming language extensions to increase accessibility and portability. However, this paper argues that new high-level programming models built on common software abstractions better address these goals. The hthreads system, in general, is unique within the reconfigurable computing community as it includes operating system and middleware layer abstractions that extend across the CPU/FPGA boundary. This enables all platform components to be abstracted into a unified multiprocessor architecture platform. Application programmers can then express their computations using threads specified from a single POSIX threads (pthreads) multithreaded application program and can then compile the threads to either run on the CPU or synthesize them to run within an FPGA. To enable this seamless framework, we have created the hardware thread interface (HWTI) component to provide an abstract, platform-independent compilation target for hardware-resident computations. The HWTI enables the use of standard thread communication and synchronization operations across the software/hardware boundary. Key operating system primitives have been mapped into hardware to provide threads running in both hardware and software uniform access to a set of sub-microsecond, minimal-jitter services. Migrating the operating system into hard-ware removes the potential bottleneck of routing all system service requests through a central CPU.