Time, clocks, and the ordering of events in a distributed system
Communications of the ACM
Achieving programming model abstractions for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip
ICPADS '07 Proceedings of the 13th International Conference on Parallel and Distributed Systems - Volume 01
Computer Organization and Design, Fourth Edition, Fourth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design)
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Much like other computing platforms in the world today, FPGAs are becoming increasingly larger and contain large amounts of reconfigurable logic. This makes FPGAs an acceptable platform for multiprocessor systems. However in today's world of FPGA computing, very limited infrastructure is available to facilitate the creation of cache coherent shared memory systems for FPGAs. This paper introduces FCache, a system for shared memory cache coherent processing on FPGAs. The paper also describes the mapping of the conventional shared bus to FPGAs using two distinct network implemented in FCache. FCache also provides flushing and multithreaded synchronization functionalities, such as locking and unlocking of a mutex variable, which is embedded in its cache component. Despite these additional functionalities, results show that FCache has little resource overhead compared to a previous more simplistic cache coherent system that was targeted for FPGAs.