The first real operating system for reconfigurable computers
ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture
μITRON for Small-Scale Embedded Systems
IEEE Micro
Automatc identification of swappable logic units in XC6200 circuitry
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A Virtual Hardware Operating System for the Xilinx XC6200
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Designing an Operating System for a Heterogeneous Reconfigurable SoC
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Real-Time System Design and Analysis
Real-Time System Design and Analysis
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
Seamless Hardware-Software Integration in Reconfigurable Computing Systems
IEEE Design & Test
REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs
Proceedings of the 3rd conference on Computing frontiers
Hard real-time reconfiguration port scheduling
Proceedings of the conference on Design, automation and test in Europe
Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
ACM Transactions on Embedded Computing Systems (TECS)
Achieving programming model abstractions for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving the efficiency of run time reconfigurable devices by configuration locking
Proceedings of the conference on Design, automation and test in Europe
Reconfigurable System Design and Verification
Reconfigurable System Design and Verification
On-line task management for a reconfigurable cryptographic architecture
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Electronic system-level synthesis methodologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Run-time HW/SW scheduling of data flow applications on reconfigurable architectures
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Rapid Application Development on Multi-processor Reconfigurable Systems
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Internal and external bitstream relocation for partial dynamic reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
FUSE: Front-End User Framework for O/S Abstraction of Hardware Accelerators
FCCM '11 Proceedings of the 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines
Hardware/Software Communication Middleware for Data Adaptable Embedded Systems
ECBS '11 Proceedings of the 2011 18th IEEE International Conference and Workshops on Engineering of Computer-Based Systems
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
Hardware OS Communication Service and Dynamic Memory Management for RSoCs
RECONFIG '11 Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs
High-Level Synthesis for FPGAs: From Prototyping to Deployment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System Level Power Characterization of Multi-core Computers with Dynamic Frequency Scaling Support
CLUSTERW '12 Proceedings of the 2012 IEEE International Conference on Cluster Computing Workshops
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Dynamic Partial Reconfiguration technology coupled with an Operating System for Reconfigurable Systems (OS4RS) allows for implementation of a hardware task concept, that is, an active computing object which can contend for reconfigurable computing resources and request OS services in a way software task does in a conventional OS. In this work, we show a complete model and implementation of a lightweight OS4RS supporting preemptable and clock-scalable hardware tasks. We also propose a novel, lightweight scheduling mechanism allowing for timely and priority-based reservation of reconfigurable resources, which aims at usage of preemption only at the time it brings benefits to the performance of a system. The architecture of the scheduler and the way it schedules allocations of the hardware tasks result in shorter latency of system calls, thereby reducing the overall OS overhead. Finally, we present a novel model and implementation of a channel-based intertask communication and synchronization suitable for software-hardware multitasking with preemptable and clock-scalable hardware tasks. It allows for optimizations of the communication on per task basis and utilizes point-to-point message passing rather than shared-memory communication, whenever it is possible. Extensive overhead tests of the OS4RS services as well as application speedup tests show efficiency of our approach.