FPGA framework for agent systems using dynamic partial reconfiguration
HoloMAS'11 Proceedings of the 5th international conference on Industrial applications of holonic and multi-agent systems for manufacturing
Elastic computing: A portable optimization framework for hybrid computers
Parallel Computing
FlexTiles: a globally homogeneous but locally heterogeneous manycore architecture
Proceedings of the 6th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
International Journal of Reconfigurable Computing
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SoCs can be implemented on a single FPGA, offering designers a unique opportunity for Embedded Systems. Instead of defining a fixed architecture early in the design process, the reconfigurable platform allows architectural redesign to meet the system's specific needs. However, the ability to instantiate new modules in the reconfigurable hardware provides a unique set of challenges for integration, particularly to the software (SW) designer. Specifically, the Operating System (OS) cannot automatically abstract these platform changes without redesign. In this paper, we present FUSE, a framework for HW accelerator abstraction that provides: 1) transparency to the SW designer at the application level, and 2) OS support for easy HW accelerator integration. We illustrate FUSE as an API for an embedded Linux OS with POSIX threads on Xilinx's Micro Blaze on a Virtex5. For three different applications and HW accelerators, we achieve performance speedups ranging from 6.4-37x.