Improving the efficiency of run time reconfigurable devices by configuration locking

Authors:
Yang Qu;Juha-Pekka Soininen;Jari Nurmi
Affiliations:
Technical Research Centre of Finland (VTT), Oulu, Finland;Technical Research Centre of Finland (VTT), Oulu, Finland;Tampere University of Technology, Tampere, Finland
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2008

Citing 5
Cited 1

Configuration Caching Management Techniques for Reconfigurable Computing

FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Instruction Scheduling for Dynamic Hardware Configurations

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison

Proceedings of the conference on Design, automation and test in Europe
Static scheduling techniques for dependent tasks on dynamically reconfigurable devices

Journal of Systems Architecture: the EUROMICRO Journal

Rainbow: an operating system for software-hardware multitasking on dynamically partially reconfigurable FPGAs

International Journal of Reconfigurable Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configuration overhead can largely decrease the system performance. In this work, we present a novel configuration locking technique to reduce the effect of the overhead. The idea is to at run-time lock a number of the most frequently used tasks on the configuration memory so that they cannot be evicted by other tasks. With real applications in validation, the results show that using proper amount of resources to lock tasks can significantly outperform simply using more resources. In addition, an algorithm has been developed for estimating the lock ratio. Experimental results show that the estimates are close to optimal results and the measured computer runtime is less than 4 us in a commercial embedded processor.