Optimal and efficient speculation-based partial redundancy elimination
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
Compiler-driven FPGA-area allocation for reconfigurable computing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration
Journal of VLSI Signal Processing Systems
Static scheduling techniques for dependent tasks on dynamically reconfigurable devices
Journal of Systems Architecture: the EUROMICRO Journal
Improving the efficiency of run time reconfigurable devices by configuration locking
Proceedings of the conference on Design, automation and test in Europe
Interprocedural optimization for dynamic hardware configurations
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
ACM Transactions on Embedded Computing Systems (TECS)
Dynamic configuration prefetching based on piecewise linear prediction
Proceedings of the Conference on Design, Automation and Test in Europe
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Although the huge reconfiguration latency of the available FPGA platforms is a well-known shortcoming of the current FCCMs, little research in instruction scheduling has been undertaken to eliminate or diminish its negative influence on performance. In this paper, we introduce an instruction scheduling algorithm that minimizes the number of executed hardware reconfiguration instructions taking into account the "FPGA area placement conflicts" between the available configurations. The algorithm is based on compiler analyses and feedback-directed techniques and it can switch from hardware execution to software execution for an operation, when the reconfiguration latency could not be reduced. The algorithm has been tested for the M-JPEG encoder application and the real hardware implementations for DCT, Quantization and VLC operations. Based on simulation results, we determine that, while a simple scheduling produces a significant performance decrease, our proposed scheduling contributes for up to 16x M-JPEG encoder speedup.