Configuration prefetch for single context reconfigurable coprocessors
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A C compiler for a processor with a reconfigurable functional unit
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Field-Programmable Custom Computing Machines - A Taxonomy -
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Configurable Systems-on-Chip (CSoC)
Proceedings of the 15th symposium on Integrated circuits and systems design
A Reconfigurable Processor Architecture and Software Development Environment for Embedded Systems
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
From C Programs to the Configure-Execute Model
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
Instruction Scheduling for Dynamic Hardware Configurations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Performance optimization of error detection based on speculative reconfiguration
Proceedings of the 48th Design Automation Conference
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In this paper, we study the performance impact of dynamic hardware reconfigurations for current reconfigurable technology. As a testbed, we target the Xilinx Virtex II Pro, the Molen experimental platform and the MPEG2 encoder as the application. Our experiments show that slowdowns of up to a factor 1000 are observed when the configuration latency is not hidden by the compiler. In order to avoid the performance decrease, we propose an interprocedural optimization that minimizes the number of executed hardware configuration instructions taking into account constraints such as the "FPGA-area placement conflicts" between the available hardware configurations. The presented algorithm allows the anticipation of hardware configuration instructions up to the application's main procedure. The presented results show that our optimization produces a reduction of 3 to 5 order of magnitude of the number of executed hardware configuration instructions. Moreover, the optimization allows to exploit up to 97% of the maximal theoretical speedup achieved by the reconfigurable hardware execution.