Optimal FPGA module placement with temporal precedence constraints
Proceedings of the conference on Design, automation and test in Europe
Priority Inheritance Protocols: An Approach to Real-Time Synchronization
IEEE Transactions on Computers
Task scheduling for heterogeneous reconfigurable computers
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Online Scheduling for Block-Partitioned Reconfigurable Devices
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
Hard Real-time Computing Systems: Predictable Scheduling Algorithms And Applications (Real-Time Systems Series)
Proceedings of the 42nd annual Design Automation Conference
The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Reconfiguration Manager for Dynamically Reconfigurable Hardware
IEEE Design & Test
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A (fault-tolerant)2 scheduler for real-time HW tasks
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Operating system for runtime reconfigurable multiprocessor systems
International Journal of Reconfigurable Computing - Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems
ACM Transactions on Embedded Computing Systems (TECS)
International Journal of Reconfigurable Computing
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When modern partially and dynamically reconfigurable FPGAs are to be used as resources in hard real-time systems, the two dimensions area and time have to be considered in the focus of availability and deadlines. In particular, area requirements must be guaranteed for the tasks' duration. While execution environments that abstract the space demand of tasks exist and methods for occupancy of resources over time are discussed in the literature, few works focus on another fundamental bottleneck, the reconfiguration port. As all resource requests are served by this mutually exclusive device, profound concepts for scheduling the port access are vital requirements for FPGA realtime scheduling. Nevertheless, as the port must be accessed sequentially, we can inherit and apply monoprocessor scheduling concepts that are well researched. In this paper, we introduce monoprocessor scheduling algorithms for the reconfiguration port of FPGAs.