Pthreads programming
Parallel programming in OpenMP
Parallel programming in OpenMP
The MOLEN rho-mu-Coded Processor
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
UltraSONIC: A Reconfigurable Architecture for Video Image Processing
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Hardware implementation of a real-time operating system
TRON '95 Proceedings of the The 12th TRON Project International Symposium, 1995
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
Run-time support for heterogeneous multitasking on reconfigurable SoCs
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
An Operating System Framework for Reconfigurable Systems
CIT '05 Proceedings of the The Fifth International Conference on Computer and Information Technology
Hardware/software partitioning of operating systems: a behavioral synthesis approach
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
An efficient algorithm for online management of 2D area of partially reconfigurable FPGAs
Proceedings of the conference on Design, automation and test in Europe
Achieving programming model abstractions for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
ReconOS: Multithreaded programming for reconfigurable computers
ACM Transactions on Embedded Computing Systems (TECS)
Reconfigurable Multithreading Architectures: A Survey
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation for Dense Matrices
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Mt-ADRES: multithreading on coarse-grained reconfigurable architecture
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Parallel FPGA-based all-pairs shortest-paths in a directed graph
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IEEE Transactions on Computers
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In this paper, we address the problem of organization and management of threads on a multithreading custom computing machine composed of a General Purpose Processor (GPP) and Reconfigurable Coprocessors. We target higher portability, flexibility, and performance of the prospective design solutions by means of a strictly architectural approach. Our proposal to improve overall system performance is twofold. First, we provide architectural mechanisms to accelerate applications by supporting computationally intensive kernels with reconfigurable hardware accelerators. Second, we propose an infrastructure capable of facilitating thread management. Besides the architectural and microarchitectural extensions of the reconfigurable computing system, we also propose a hierarchical programming model. The model supports balanced and performance efficient SW/HW co-execution of multithreading applications. We demonstrate that our approach provides better performance-portability and performance-flexibility trade-off characteristics compared to other state-of-the-art proposals. The experimental results, based on real applications, suggest average system speedups between 1.2 and 19.6. Based on singlethreaded synthetic benchmark, we achieve average speedup between 8.5 and 129. For multithreaded synthetic benchmark, the achieved average speedup is between 1.3 and 7.3.