Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
An efficient algorithm for finding empty space for online FPGA placement
Proceedings of the 41st annual Design Automation Conference
An efficient algorithm for free resources management on the FPGA
Proceedings of the conference on Design, automation and test in Europe
Intelligent merging online task placement algorithm for partial reconfigurable systems
Proceedings of the conference on Design, automation and test in Europe
Microprocessors & Microsystems
Server-side coprocessor updating for mobile devices with FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Architectural support for multithreading on reconfigurable hardware
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
A new metric for on-line scheduling and placement in reconfigurable computing systems
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
Multithreading on reconfigurable hardware: An architectural approach
Microprocessors & Microsystems
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Partially Runtime-Reconfigurable (PRTR) FPGAs allow hardware tasks to be placed and removed dynamically at runtime. We present an efficient algorithm for finding the complete set of maximal empty rectangles on a 2D PRTR FPGA, which is useful for online placement and scheduling of HW tasks. The algorithm is incremental and only updates the local region affected by each task addition or removal event. We use simulation experiments to evaluate its performance and compare to related work.