Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
An efficient algorithm for finding empty space for online FPGA placement
Proceedings of the 41st annual Design Automation Conference
An efficient algorithm for online management of 2D area of partially reconfigurable FPGAs
Proceedings of the conference on Design, automation and test in Europe
Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Online scheduling for multi-core shared reconfigurable fabric
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Finding the available empty space for arrival tasks on FP-GAs with runtime partially reconfigurable abilities is the most time consuming phase in on-line placement algorithms. Naturally, this phase has the highest impact on the overall system performance. In this paper, we present a new algorithm which is used to find the complete set of maximum free rectangles on the FPGA at runtime. During scanning, our algorithm relies on dynamic information about the edges of all already placed tasks. Simulation results show that our algorithm has 1.5x to 5x speedup compared to state of the art algorithms aiming at maximum free rectangles. In addition, our proposal requires at least 4.4x less scanning load.