Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
Developments from a June 1996 seminar on Online algorithms: the state of the art
Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
An efficient algorithm for finding empty space for online FPGA placement
Proceedings of the 41st annual Design Automation Conference
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An efficient algorithm for online management of 2D area of partially reconfigurable FPGAs
Proceedings of the conference on Design, automation and test in Europe
A reconfigurable computing platform for real time embedded applications
Microprocessors & Microsystems
Hi-index | 0.00 |
Partial Runtime Reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. We make two contributions in this paper. First, we present an efficient algorithm for finding the complete set of Maximal Empty Rectangles on a 2D PRTR FPGA. We also present a HW implementation of the algorithm with negligible runtime overhead. Second, we present an efficient online deadline-constrained task placement algorithm for minimizing area fragmentation on the FPGA by using an area fragmentation metric that takes into account probability distribution of sizes of future task arrivals as well as the time axis. The techniques presented in this paper are useful in an operating system for runtime reconfigurable FPGAs to manage the HW resources on the FPGA when HW tasks that arrive and finish dynamically at runtime.