SUIF: an infrastructure for research on parallelizing and optimizing compilers
ACM SIGPLAN Notices
Page replacement with multi-size pages and applications to Web caching
STOC '97 Proceedings of the twenty-ninth annual ACM symposium on Theory of computing
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Configuration prefetch for single context reconfigurable coprocessors
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Configuration Compression for the Xilinx XC6200 FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
On-Line File Caching
Cost-aware WWW proxy caching algorithms
USITS'97 Proceedings of the USENIX Symposium on Internet Technologies and Systems on USENIX Symposium on Internet Technologies and Systems
A study of replacement algorithms for a virtual-storage computer
IBM Systems Journal
Improving Code Efficiency for Reconfigurable VLIW Processors
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
A Performance Model for Run-Time Reconfigurable Hardware Accelerator
APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
Reconfigurable computing and task scheduling for active storage service processing
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
A configuration system architecture supporting bit-stream compression for FPGAs
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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Speedups of coupled processor-FPGA systems over traditional microprocessor systems are limited by the cost of hardware reconfiguration. In this paper we compare several new configuration caching algorithms that reduce the latency of reconfiguration. We also present a cache replacement strategy for a 3-level hierarchy. Using the techniques we present, total latency for loading the configurations is reduced, lowering the configurable overhead.