IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
MIPS RISC architectures
Inside Windows NT
Architectural support for translation table management in large address space machines
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Design tradeoffs for software-managed TLBs
ACM Transactions on Computer Systems (TOCS)
Performance of the VAX-11/780 translation buffer: simulation and measurement
ACM Transactions on Computer Systems (TOCS)
SOSP '95 Proceedings of the fifteenth ACM symposium on Operating systems principles
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
A look at several memory management units, TLB-refill mechanisms, and page table organizations
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Software-Managed Address Translation
HPCA '97 Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture
The multics system: an examination of its structure
The multics system: an examination of its structure
A look at several memory management units, TLB-refill mechanisms, and page table organizations
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Main-memory index structures with fixed-size partial keys
SIGMOD '01 Proceedings of the 2001 ACM SIGMOD international conference on Management of data
Uniprocessor Virtual Memory without TLBs
IEEE Transactions on Computers
Characterizing the d-TLB behavior of SPEC CPU2000 benchmarks
SIGMETRICS '02 Proceedings of the 2002 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers
HiPC '01 Proceedings of the 8th International Conference on High Performance Computing
Configuration Caching and Swapping
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Two-Level Address Storage and Address Prediction (Research Note)
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
A banked-promotion translation lookaside buffer system
Journal of Systems Architecture: the EUROMICRO Journal
Configurable parallel memory architecture for multimedia computers
Journal of Systems Architecture: the EUROMICRO Journal
A selective filter-bank TLB system
Proceedings of the 2003 international symposium on Low power electronics and design
In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs)
IEEE Transactions on Computers
Deconstructing process isolation
Proceedings of the 2006 workshop on Memory system performance and correctness
Integrating research and e-learning in advanced computer architecture courses
WCAE '04 Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture
DLL-conscious instruction fetch optimization for SMT processors
Journal of Systems Architecture: the EUROMICRO Journal
Inter-core cooperative TLB for chip multiprocessors
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
Efficient virtual memory for big memory servers
Proceedings of the 40th Annual International Symposium on Computer Architecture
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This article presents a survey of commercial memory-management designs and describes how each processor architecture supports the common features of virtual memory, such as address space protection, shared memory, and large address spaces.