Tradeoffs in supporting two page sizes
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Optimally profiling and tracing programs
ACM Transactions on Programming Languages and Systems (TOPLAS)
Surpassing the TLB performance of superpages with less operating system support
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
High-bandwidth address translation for multiple-issue processors
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Analytical energy dissipation models for low-power caches
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Reducing TLB power requirements
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
The filter cache: an energy efficient memory structure
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Energy-Efficiency of VLSI Caches: A Comparative Study
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
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We present a simple but high performance translation lookaside buffer (TLB) system with low power consumption for use in embedded systems. Our TLB structure supports two page sizes dynamically and selectively to achieve high performance with low hardware cost. To minimize power consumption, a banked-TLB is constructed by dividing one fully associative (FA) TLB space into two separate FA TLBs. These two structures are integrated to form a banked-promotion (BP) TLB. Promotion overcomes the unbalanced utilization of a banked-TLB by moving adjacent entries out of the primary banks into a separate super-page TLB. Simulation results show that the Energy* Delay product can be reduced by about 99.8%, 19.2%, 24.2%, and 24.4% compared with a FA TLB, a micro-TLB, a banked-TLB, and a victim-TLB respectively. Therefore, the BP TLB offers high performance with low power consumption and low hardware cost.