Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Code generation using tree matching and dynamic programming
ACM Transactions on Programming Languages and Systems (TOPLAS)
The Garp Architecture and C Compiler
Computer
Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
A Concept for an Evaluation Framework for Reconfigurable Systems
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Configuration Caching and Swapping
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
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High code efficiency (operations per instruction) combined with a high degree of instruction level parallelism can rarely be obtained by hardwired microprocessor designs for a broad application domain. The implementation of reconfigurable execution units is a promising way to enhance code efficiency and microprocessor performance. However, the unit reconfiguration process introduces an additional dimension to the code generation phase, which complicates scheduling and may lead to code deficiencies if resource conflicts occure. This paper discusses code generation issues for a runtime-reconfigurable VLIW processor model, which combines fixed and flexible functional units (FU) in one template. Reconfigurable units (RFU) can be adapted to the application demands exploiting more coarse-grain parallelism than common instruction-level FUs. A case study illustrates the extraction of conditions for reconfigurable instructions proves scheduling possibilities for a set of common DSP benchmark algorithms. The software environment described includes a retargetable, parallelizing C compiler based on the SUIF compiler kit and a simulator, which can be used for identifying application-specific SIMD-instruction candidates and for evaluating the runtime behavior of the created object code.