Optimal synthesis of multichip architectures
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
An optimal methodology for synthesis of DSP multichip architectures
Journal of VLSI Signal Processing Systems - Special issue on VLSI design methodologies for digital signal processing systems
Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Network flow based circuit partitioning for time-multiplexed FPGAs
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An efficient list scheduling algorithm for time placement problem
Computers and Electrical Engineering
Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices
IEEE Transactions on Computers
Temporal partitioning data flow graphs for dynamically reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Eigenvalue Bounds, Spectral Partitioning, and Metrical Deformations via Flows
FOCS '08 Proceedings of the 2008 49th Annual IEEE Symposium on Foundations of Computer Science
IEEE Transactions on Computers
Network-flow-based multiway partitioning with area and pin constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generic ILP-based approaches for time-multiplexed FPGA partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we present a typical temporal partitioning methodology that temporally partitions a data flow graph on reconfigurable system. Our approach optimizes the communication cost of the design. This aim can be reached by minimizing the transfer of data required between design partitions and the routing cost between FPGA modules. Consequently, our algorithm is composed by two main steps. The first step aims to find a temporal partitioning of the graph. This step gives the optimal solution in term of communication cost. Next, our approach builds the best architecture, on a partially reconfigurable FPGA, that gives the lowest routing cost between modules. The proposed methodology was tested on several examples on the Xilinx Virtex-II pro. The results show significant reduction in the communication cost compared with others famous approaches used in this field.