FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Dynamic Precision Management for Loop Computations on Reconfigurable Architectures
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Configuration Caching Management Techniques for Reconfigurable Computing
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Performance and Overhead in a Hybrid Reconfigurable Computer
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Design methodologies for partially reconfigured systems
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Analytical modeling of high performance reconfigurable computers: prediction and analysis of system performance
Guest Editors' Introduction: Identity Management
IEEE Internet Computing
Metropolitan Road Traffic Simulation on FPGAs
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Reconfigurable computing with multiscale data fusion for remote sensing
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Families of FPGA-based accelerators for approximate string matching
Microprocessors & Microsystems
Runtime Partial Reconfiguration for Embedded Vector Processors
ITNG '07 Proceedings of the International Conference on Information Technology
Exploiting processing locality for adaptive computing systems
Exploiting processing locality for adaptive computing systems
VAPRES: a virtual architecture for partially reconfigurable embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Space and time sharing of reconfigurable hardware for accelerated parallel processing
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture
Journal of Systems Architecture: the EUROMICRO Journal
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
pvFPGA: accessing an FPGA-based hardware accelerator in a paravirtualized environment
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
The Journal of Supercomputing
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Runtime Reconfiguration (RTR) has been traditionally utilized as a means for exploiting the flexibility of High-Performance Reconfigurable Computers (HPRCs). However, the RTR feature comes with the cost of high configuration overhead which might negatively impact the overall performance. Currently, modern FPGAs have more advanced mechanisms for reducing the configuration overheads, particularly Partial Runtime Reconfiguration (PRTR). It has been perceived that PRTR on HPRC systems can be the trend for improving the performance. In this work, we will investigate the potential of PRTR on HPRC by formally analyzing the execution model and experimentally verifying our analytical findings by enabling PRTR for the first time, to the best of our knowledge, on one of the current HPRC systems, Cray XD1. Our approach is general and can be applied to any of the available HPRC systems. The paper will conclude with recommendations and conditions, based on our conceptual and experimental work, for the optimal utilization of PRTR as well as possible future usage in HPRC.