Design patterns: elements of reusable object-oriented software
Design patterns: elements of reusable object-oriented software
Algorithms on strings, trees, and sequences: computer science and computational biology
Algorithms on strings, trees, and sequences: computer science and computational biology
Hardware reuse at the behavioral level
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Application of Software design patterns to DSP library design
Proceedings of the 14th international symposium on Systems synthesis
Agile Software Development: Principles, Patterns, and Practices
Agile Software Development: Principles, Patterns, and Practices
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Application of design patterns for hardware design
Proceedings of the 40th annual Design Automation Conference
A Programmable Processor for Approximate String Matching with High Throughput Rate
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Design Patterns for Reconfigurable Computing
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Lamp: tools for creating application-specific fpga coprocessors
Lamp: tools for creating application-specific fpga coprocessors
ASC: a stream compiler for computing with FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Single pass streaming BLAST on FPGAs
Parallel Computing
Performance bounds of partial run-time reconfiguration in high-performance reconfigurable computing
HPRCTA '07 Proceedings of the 1st international workshop on High-performance reconfigurable computing technology and applications: held in conjunction with SC07
Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Using Reconfigurable Supercomputers and C-to-Hardware Synthesis for CNN Emulation
IWINAC '09 Proceedings of the 3rd International Work-Conference on The Interplay Between Natural and Artificial Computation: Part II: Bioinspired Applications in Artificial and Natural Computation
Reducing storage requirements in accelerating algorithm of global BioSequence alignment on FPGA
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Protein similarity search with subset seeds on a dedicated reconfigurable hardware
PPAM'07 Proceedings of the 7th international conference on Parallel processing and applied mathematics
Hardware accelerated sequence alignment with traceback
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
FPGA-based smith-waterman algorithm: analysis and novel design
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
A pipelined processor architecture for regular expression string matching
Microprocessors & Microsystems
Optimization schemes and performance evaluation of Smith–Waterman algorithm on CPU, GPU and FPGA
Concurrency and Computation: Practice & Experience
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Dynamic programming for approximate string matching is a large family of different algorithms, which vary significantly in purpose, complexity, and hardware utilization. Many implementations have reported impressive speed-ups, but have typically been point solutions - highly specialized and addressing only one or a few of the many possible options. The problem to be solved is creating a hardware description that implements a broad range of behavioral options without losing efficiency due to feature bloat. We report a set of three component types that address different parts of the approximate string matching problem. This allows each application to choose the feature set required, then make maximum use of the FPGA fabric according to that application's specific resource requirements. Multiple, interchangeable implementations are available for each component type. We show that these methods allow the efficient generation of a large, if not complete, family of accelerators for this application. This flexibility was obtained while retaining high performance: we have evaluated a sample against serial reference codes and found speed-ups of from 150x to 400x over a high-end PC.