DESIGN OF A HIGH SPEED STRING MATCHING CO-PROCESSOR FOR NLP
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A recursive MISD architecture for pattern matching
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Families of FPGA-based accelerators for approximate string matching
Microprocessors & Microsystems
Single pass streaming BLAST on FPGAs
Parallel Computing
A fast scalable automaton-matching accelerator for embedded content processors
ACM Transactions on Embedded Computing Systems (TECS)
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In this paper, we present the algorithm and architecture of a processor for approximate string matching with high throughput rate. The processor is dedicated for multimedia and information retrieval applications working on huge amounts of mass data where short response times are necessary. The algorithm used for the approximate string matching is based on a dynamic programming procedure known as the string-to-string correction problem. It has been extended to fulfill the requirements of full text search in a database system, including string matching with wildcards and handling of idiomatic turns of some languages. The processor has been fabricated in a 0.6-um CMOS technology. It performs a maximum of 8.5 Billion character comparisons per second when operating at the specified clock frequency of 132 MHz.