A pipelined processor architecture for regular expression string matching

Authors:
Qiyue Li;Jie Li;Jianping Wang;Baohua Zhao;Yugui Qu
Affiliations:
School of Electric Engineering and Automation, Hefei University of Technology, Hefei, Anhui 230009, China;School of Computer and Information, Hefei University of Technology, Hefei, Anhui 230009, China;School of Electric Engineering and Automation, Hefei University of Technology, Hefei, Anhui 230009, China;Dept. of Computer Science and Technology, University of Science and Technology of China, Hefei, Anhui 230027, China and State Key Laboratory of Networking and Switching Technology, Beijing 100876, ...;Dept. of Electronic Engineering & Information Science, University of Science and Technology of China, Hefei, Anhui 230027, China
Venue:
Microprocessors & Microsystems
Year:
2012

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Abstract

The expressive power of regular expressions has been often adopted in network intrusion detection systems, virus scanners, and spam filtering applications. However in the CPU based systems, pattern matching is one of the most computation intensive parts. In this paper, we present the design, implementation and evaluation of a regular expression string matching processing unit (SMPU). This special purpose processor is a parallel and pipelined architecture which can deal with the regular expression semantics. Two hardware stacks are implemented in SMPU to support fast branches when the non-matching occurs. Our implementation processes four characters per clock cycle (maximum performance of state of the art solutions) and occupies only O(n) memory (where n is the length of the regular expression) via synthesizing the verilog description and analyzing area/time constraints, SMPU can achieve 200-400 times speedup over traditional CPU implementations and up to 7.9Gbps in processing throughput. Besides it outperforms the counterparts greatly as the complexity of regular expressions increases.