Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Incorporating cores into system-level specification
Proceedings of the 11th international symposium on System synthesis
An MPEG-2 decoder case study as a driver for a system level design methodology
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
The case for a configure-and-execute paradigm
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Power estimation for architectural exploration of HW/SW communication on system-level buses
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Adapting cache line size to application behavior
ICS '99 Proceedings of the 13th international conference on Supercomputing
Interface and cache power exploration for core-based embedded system design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A hybrid approach for core-based system-level power modeling
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Introducing Core-Based System Design
IEEE Design & Test
Coding a terminated bus for low power
GLSVLSI '95 Proceedings of the Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
Parameterised system design based on genetic algorithms
Proceedings of the ninth international symposium on Hardware/software codesign
Functional abstraction driven design space exploration of heterogeneous programmable architectures
Proceedings of the 14th international symposium on Systems synthesis
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Safe integration of parameterized IP
Integration, the VLSI Journal - Special issue: IP and design reuse
Families of FPGA-based accelerators for approximate string matching
Microprocessors & Microsystems
Optimal allocation of I/O device parameters in hardware and software codesign methodology
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
Journal of Electronic Testing: Theory and Applications
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Continued growth in chip capacity has led to new methodologies stressing reuse, not only of pre-designed processing components, but even of entire pre-designed architectures. To be used across a variety of applications, such architectures must be heavily parameterized, so they can adapt to those applications' differing constraints by trading off power, performance and size. We describe several parameterized system design issues, and provide results showing how a single architecture with easily configurable parameters can support a wide range of tradeoffs.