Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
A processor desription language supporting retargetable multi-pipeline DSP program development tools
Proceedings of the 11th international symposium on System synthesis
Fast prototyping: a system design flow for fast design, prototyping and efficient IP reuse
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
An efficient reuse system for digital circuit design
DATE '99 Proceedings of the conference on Design, automation and test in Europe
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
On the roles of functions and objects in system specification
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Linking codesign and reuse in embedded systems design
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
A framework for fast hardware-software co-simulation
Proceedings of the conference on Design, automation and test in Europe
A systematic analysis of reuse strategies for design of electronic circuits
Proceedings of the conference on Design, automation and test in Europe
Processor Modeling for Hardware Software Codesign
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Microarchitectural exploration with Liberty
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Proceedings of the 40th annual Design Automation Conference
Optimizations for a simulator construction system supporting reusable components
Proceedings of the 40th annual Design Automation Conference
Graph-Based Functional Test Program Generation for Pipelined Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Top-Down Methodology for Microprocessor Validation
IEEE Design & Test
A novel approach for flexible and consistent ADL-driven ASIP design
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations
IEEE Transactions on Computers
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An integrated open framework for heterogeneous MPSoC design space exploration
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Automatic instruction scheduler retargeting by reverse-engineering
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
The Liberty Simulation Environment: A deliberate approach to high-level system modeling
ACM Transactions on Computer Systems (TOCS)
Achieving structural and composable modeling of complex systems
International Journal of Parallel Programming - Special issue: The next generation software program
Retargetable code optimization with SIMD instructions
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Application-specific customization of parameterized FPGA soft-core processors
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2007 Summer Computer Simulation Conference
Specification-driven directed test generation for validation of pipelined processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Retargetable code optimization for predicated execution
Proceedings of the conference on Design, automation and test in Europe
Processor Description Languages
Processor Description Languages
A SIMD optimization framework for retargetable compilers
ACM Transactions on Architecture and Code Optimization (TACO)
Automatic ADL-based assembler generation for ASIP programming support
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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Rapid Design Space Exploration (DSE) of a programmable architecture is feasible using an automatic toolkit (compiler, simulator, assembler) generation methodology driven by an Architecture Description Language (ADL). While many contemporary ADLs can effectively capture one class of architecture, they are typically unable to capture a wide spectrum of processor and memory features present in DSP, VLIW, EPIC and Superscalar processors. The main bottleneck has been the lack of an abstraction underlying the ADL (covering a diverse set of architectural features) that permits reuse of the abstraction primitives to compose the heterogeneous architectures. We present in this paper the functional abstraction needed to capture such wide variety of programmable architectures. We illustrate the usefulness of this approach by specifying two very different architectures using functional abstraction. Our DSE results demonstrate the power of reuse in composing heterogeneous architectures using functional abstraction primitives allowing for a reduction in the time for specification and exploration by at least an order of magnitude.