Space and time sharing of reconfigurable hardware for accelerated parallel processing

Authors:
Esam El-Araby;Vikram K. Narayana;Tarek El-Ghazawi
Affiliations:
NSF Center for High-Performance Reconfigurable Computing (CHREC), The George Washington University, Washington, DC;NSF Center for High-Performance Reconfigurable Computing (CHREC), The George Washington University, Washington, DC;NSF Center for High-Performance Reconfigurable Computing (CHREC), The George Washington University, Washington, DC
Venue:
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Year:
2010

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Abstract

High-Performance Reconfigurable Computers (HPRCs) are parallel machines consisting of FPGAs and microprocessors, with the FPGAs used as co-processors. The execution of parallel applications on such systems has mainly followed the Single-Program Multiple-Data (SPMD) model; however, overall system resources are often underutilized because of the asymmetric distribution of the reconfigurable (co-)processors relative to the (main) processors. Furthermore, with the introduction of HPRCs containing multi/many-core technologies, underutilization of system resources becomes more obvious especially for multi-tasking and multi-user usage. To address the asymmetry problem, we propose a resource virtualization solution based on Partial Run-Time Reconfiguration (PRTR). The proposed technique allows space, time, and/or space-time sharing of the reconfigurable (co-)processors among the (main) processors and thus increasing the overall system utilization. We show the effectiveness of the proposed concepts through a stochastic execution model verified with experimental implementations on the Cray XD1 platform. The results demonstrate favorable performance as well as scalability characteristics.