Macro-instruction generation for dynamic logic caching

Authors:
K. McCarley;S. B. K. Vrudhula
Affiliations:
-;-
Venue:
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
Year:
1997

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Abstract

This paper outlines the synthesis of macro-instructions for dynamically reprogrammable FPGAs so that they may be easily generated, placed, and garbage collected at run-time. An overview of a dynamic logic caching computer that uses these macro-instructions is given and their use within the's environment discussed. The synthesis of macro-instructions is illustrated with a basic example. Finally, the current state of development of a logic cache based computing platform and compiler/simulator workframe is presented.