A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs

Authors:
Manish Handa;Rajesh Radhakrishnan;Madhubanti Mukherjee;Ranga Vemuri
Affiliations:
-;-;-;-
Venue:
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Year:
2003

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Abstract

In this paper, we propose a methodology for automatedmapping of a design onto a partially reconfigurable device.We generate partial bitstream files from behavioral descriptionof the task, that are used to reconfigure the device dynamically.The novelty of this research lies in the applicationof a Macro Based Synthesis approach that allowselimination of both logic synthesis and technology mappingphases from the synthesis flow. Our methodology provides asignificant reduction in compilation time compared to commercialtools.