Design and Implementation of Viterbi Decoder with FPGAs
Journal of VLSI Signal Processing Systems
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
Design and Implementation of Viterbi Decoder Using FPGAs
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Hidden Markov modeling and fuzzy controllers in FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations
Journal of VLSI Signal Processing Systems
Reducing leakage energy in FPGAs using region-constrained placement
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
A design flow for partially reconfigurable hardware
ACM Transactions on Embedded Computing Systems (TECS)
A Game Theoretic Approach to Dynamic Energy Minimization in Wireless Transceivers
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey
Journal of VLSI Signal Processing Systems
A reconfigurable, power-efficient adaptive Viterbi decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Run-time reconfigurable systems for digital signal processing applications: a survey
Journal of VLSI Signal Processing Systems
Temporal floorplanning using the three-dimensional transitive closure subGraph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FPGA implementation of Viterbi decoder
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
FPGA implementation of Viterbi decoder
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Dynamic reconfiguration in JPEG2000 hardware architecture
KES'11 Proceedings of the 15th international conference on Knowledge-based and intelligent information and engineering systems - Volume Part III
Dynamic partial reconfigurable Viterbi decoder for wireless standards
Computers and Electrical Engineering
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The use of error-correcting codes has proven to be an effective way to overcome data corruption in digital communication channels. Although widely-used, the most popular communications decoding algorithm, the Viterbi algorithm, requires an exponential increase in hardware complexity to achieve greater decode accuracy. In this paper, we describe the analysis and implementation of a reduced-complexity decode approach, the adaptive Viterbi algorithm (AVA). Our AVA design is implemented in reconfigurable hardware to take full advantage of algorithm parallelism and specialization. Run-time dynamic reconfiguration is used in response to changing channel noise conditions to achieve improved decoder performance. Implementation parameters for the decoder have been determined through simulation and the decoder has been implemented on a Xilinx XC4036-based PCI board. An overall decode performance improvement of 7.5X for AVA has been achieved versus algorithm implementation on a Celeron-processor based system. The use of dynamic reconfiguration leads to a 20% performance improvement over a static implementation with no loss of decode accuracy.