Design and Implementation of Viterbi Decoder with FPGAs

Authors:
M. Kivioja;J. Isoaho;L. Vänskä
Affiliations:
Tampere University of Technology, Digital Media Institute, P.O. Box 553 FIN-33101 Tampere, Finland;The Royal Institute of Technology, Electronic System Design, Department of Electronics, SE-164 40 Kista, Sweden;Nokia Research Center, P.O. Box 45, FIN-00211 Helsinki, Finland
Venue:
Journal of VLSI Signal Processing Systems
Year:
1999

Citing 4
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Abstract

In this paper we present our studies forimplementing complex DSP and Telecom systems in FPGAs. Weanalyse suitability of FPGA device architectures for implementingcomplex algorithms. Here we use a Viterbi algorithm as a deeper casestudy. Different architectural strategies for implementations arediscussed and analysed with the special emphasis on practical FPGAimplementations. Speed performance, easy routability and minimisationof inter-chip communication are used as design criteria. Viterbidecoder, constraint length seven, was designed and simulated with VHDLin Synopsys and Mentor tool environments and further implemented onfour Xilinx 4028EX devices using trace-back based architecture. Also partitioning aspects of the decoding algorithm are presented andanalysed.