FPGA implementation of Viterbi decoder

Authors:
S. Hema;V. Suresh Babu;P. Ramesh
Affiliations:
Dept of ECE, College of Engineering Trivandrum, Kerala University, Trivandrum, Kerala, India;Dept of ECE, College of Engineering Trivandrum, Kerala University, Trivandrum, Kerala, India;Dept of ECE, College of Engineering Trivandrum, Kerala University, Trivandrum, Kerala, India
Venue:
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Year:
2007

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Abstract

Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. The Viterbi algorithm, which is the most extensively employed decoding algorithm for convolutional codes. In this paper, we present a field-programmable gate array implementation of Viterbi Decoder with a constraint length of 11 and a code rate of 1/3. It shows that the larger the constraint length used in a convolutional encoding process, the more powerful the code produced.