An implicit connection graph maze routing algorithm for ECO routing
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Physical Design for 3D System on Package
IEEE Design & Test
An-OARSMan: obstacle-avoiding routing tree construction with good length performance
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Thermal-aware Steiner routing for 3D stacked ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
FPGA implementation of Viterbi decoder
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Computational Geometry: Algorithms and Applications
Computational Geometry: Algorithms and Applications
An efficient rectilinear Steiner tree algorithm with obstacles
CSECS'06 Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing
An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In recent years, scaling down device dimension or utilizing novel crystallization technologies provide the opportunity of applying much more devices to integrated circuit fabrication. Due to emerging DSM effects, the research about routing has drawn much attention in VLSI Physical Design. In this paper, we will focus on three issues. One, the traditional Manhattan routing has longer length and larger delay than X-Architecture routing. Second, in multilayer routing, the delay of one via is much larger than the delay of Manhattan routing. Third, since a routed segment and macro cell should be considered as obstacles, we must consider the rectangle and non-rectangle obstacles, and consider the number of vias as well. Our algorithm can handle both rectangle obstacles and non-rectangle obstacles, and we use fewer vias and X-Architecture router by region to construct the multilayer routing trees. The main purpose is to obtain an obstacles-avoiding routing tree of minimal wire length and minimal delay.