Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles
IEEE Transactions on Computers
Optimal two-terminal &agr;-&bgr; wire routing
Integration, the VLSI Journal
A gridless router for industrial design rules
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
An interactive maze router with hints
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Maze router without a grid map
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
DAC '84 Proceedings of the 21st Design Automation Conference
Finding obstacle-avoiding shortest paths using implicit connection graphs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DUNE: a multi-layer gridless routing system with wire planning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Pseudo pin assignment with crosstalk noise control
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A boolean satisfiability-based incremental rerouting approach with application to FPGAs
Proceedings of the conference on Design, automation and test in Europe
A minimum cost path search algorithm through tile obstacles
Proceedings of the 2001 international symposium on Physical design
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Multilevel approach to full-chip gridless routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Optimal buffered routing path constructions for single and multiple clock domain systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An efficient tile-based ECO router with routing graph reduction and enhanced global routing flow
Proceedings of the 2005 international symposium on Physical design
A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proceedings of the 2006 international symposium on Physical design
A multi-layer obstacles-avoiding router using X-architecture
WSEAS Transactions on Circuits and Systems
A metal-only-ECO solver for input-slew and output-loading violations
Proceedings of the 2009 international symposium on Physical design
A metal-only-ECO solver for input-slew and output-loading violations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SIAR: splitting-graph-based interactive analog router
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Gridless pin access in detailed routing
Proceedings of the 48th Design Automation Conference
BonnRoute: Algorithms and data structures for fast and good VLSI routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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ECO routing is a very important design capability in advanced IC, MCM and PCB designs when additional routings need to be made at the latter stage of the physical design. ECO is difficult in two aspects: first, there are a large number of existing interconnects which become obstacles in the region. A hierarchical approach is not applicable in this situation, and we need to search a large, congested region thoroughly. Second, advances in circuit designs require variable width and variable spacing on interconnects. Thus, a gridless routing algorithm is needed. In this paper, we propose to use an implicit representation of a non-uniform grid graph for gridless maze routing algorithm. A novel slit-tree plus interval-tree data structure is developed, combined with a cache structure, to support efficient queries into the connection graph. Our experiments show that this data structure is very small in memory usage while very fast in answering maze expansion related queries. This make the framework very useful in the ECO type of routing.