Introduction to algorithms
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
ISPD '00 Proceedings of the 2000 international symposium on Physical design
An implicit connection graph maze routing algorithm for ECO routing
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Efficient on-line testing of FPGAs with provable diagnosabilities
Proceedings of the 41st annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Incremental physical CAD is encountered frequently in the so-calledengineering change order (ECO) process in which design changes aremade typically late in the design process in order to correctlogical and/or technological problems in the circuit. Incrementalrouting is a significant part of an incremental physical designmethodology. Typically after an ECO process, a small portion of thecircuit netlist is changed, and in order to capitalize on theenormous resources and time already spent on routing the circuit itis desirable to reroute only the ECO-affected portion of thecircuit, while minimizing any routing changes in the much largerunaffected part. Incremental rerouting also needs to be fast and toeffectively use available routing resources. In this article, wedevelop a complete incremental routing methodology for FPGAs usinga novel approach called bump and refit (B&R). The basic B&Ridea (which was originally proposed in Dutt et al. [1999] in themuch simpler context of extending some nets by a segment for thepurpose of fault tolerance) in our algorithms is to rearrange someportions of some existing nets on other tracks within their currentchannels in order to find valid routings for the new/modified netswithout requiring any extra routing resources and with littleeffect on the electrical properties of existing nets. Here wesignificantly extend the B&R concept to global and detailedincremental routing for FPGAs with complex switchboxes (SBox's)such as those in Lucent's ORCA and Xilinx's Virtex series. Weintroduce new concepts such as a B&R cost in global routing andthe optimal subnet set to relocate for each bumped net (determinedusing an efficient dynamic programming formulation). We developedoptimal and near-optimal algorithms (called Subsec_B&R andSubnet_B&R, respectively) to find incremental routing solutionsusing the B&R paradigm in complex FPGAs (e.g.,Lucent's ORCA FPGA) withi-to-j SBox's, as well as anoptimal version Fullnet_B&R for the VPR architecture from theUniversity of Toronto using the simpleri-to-i SBox's. Wecompared our algorithms (simply called B&R when no distinctionneeds to be made between our versions) to two recent incrementalrouting techniques, Standard (Std) and Rip-up&Reroute(R&R), and to Lucent's A_PAR routing tool and the University ofToronto's VPR router used in complete rerouting modes. Experimentalresults for the ORCA show that B&R is 10 to 20 times fasterthan complete rerouting using A_PAR, and that B&R is alsonearly 27% faster and yields new nets with nearly10% smaller lengths compared to previous incrementalrouters. Furthermore, B&R routers do not change either thelengths or topologies of existing nets, a significant advantage inECO applications, in contrast to R&R which increases the lengthof ripped-up nets by an average of 8.75 to 13.6%.Experimental results for the VPR architecture are dominated by thesignificantly larger (in many cases, orders of magnitude more)number of nets left unrouted by Std and R&R compared toB&R, which highlights the much greater efficacy ofB&R-based incremental routing. However, B&R issignificantly slower than the other two incremental routers,although on an absolute scale it is quite fast for two of fourcases we simulated; in one case, it is about 25 times faster thanVPR used in the full rerouting mode. The relative slowness ofB&R for the VPR architecture arises from the fact that we usedi-to-i SBox's whichforces each net to be routed on the same track, thus causingsignificantly more bumpings and searches for rearranged solutionscompared to i-to-jSBox's where a net can be routed on differentinterconnected tracks to minimize the amount of bumpings (as we didfor the ORCA). Since modern FPGAs generally have the latter type ofSBox's, B&R would be fast as well as very effective onthem.