Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
ROAD: An Order-Impervious Optimal Detailed Router for FPGAs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
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We have developed a hop-based complete detailed router ROAD-HOP that uses the Bump & Refit (B&R) approach to route a FPGA circuit in a near-optimal manner. This approach is based on generating a minimum-spanning tree (MST) from the complete pin-to-pin graph of each net with each edge cost based on a combination of its contribution to the net length, channel congestion and potential average "bumping" cost in the channels in which the edge lies. Using the MST, a hop-based routing of each net is performed that attempts to minimize the combination of net length, number of hops and total number of tracks needed in the FPGA. Given each net's global route, a FPGA detailed router can minimize net delays by minimizing the number of hops or equivalently the number of track switchings in complex switchboxes of current FPGAs---hop-based routing can model routing using complex switchboxes. By minimizing the number of hops and total net length, ROAD-HOP minimizes net delay. Note that ROAD-HOP can only be compared to another detailed router and we compare it to the best previous detailed router SEGA for the VPR architecture. We use the output of the VPR global router as input to both ROAD-HOP and SEGA. Our new algorithm achieves significantly better results than SEGA with respect to the number of tracks needed and the circuit speed. Across a number of benchmark circuits, our algorithm needs about 8% fewer tracks than SEGA. Furthermore, the average net delay of the routing generated by our algorithm is 34% less than that of SEGA, and is 52% less for the longest net.