Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
Low overhead fault-tolerant FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On Routability for FPGAs under Faulty Conditions
IEEE Transactions on Computers
Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
A boolean satisfiability-based incremental rerouting approach with application to FPGAs
Proceedings of the conference on Design, automation and test in Europe
Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors
IEEE Transactions on Computers
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance Penalty for Fault Tolerance in Roving STARs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Efficient on-line testing of FPGAs with provable diagnosabilities
Proceedings of the 41st annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Progress in autonomous fault recovery of field programmable gate arrays
ACM Computing Surveys (CSUR)
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The ability to reconfigure around manufacturing defects and operational faults increases FPGA chip yield, reduces system downtime and maintenance in field operation, and increases reliabilities of mission- and life-critical systems. The fault reconfiguration technique discussed in this work use the principle of node covering in which reconfiguration is achieved by constructing replacement chains of cells from faulty cells to spare/unused ones. A key issue in such reconfiguration is efficient incremental rerouting in the FPGA. Previous methods for node-covering based reconfiguration are “static” in the sense that extra interconnects are added a-priori as part of the initial circuit routing so that a specific fault pattern (e.g., one fault per row) can be tolerated [1]. This, however, results in worst-case track overheads and also in an inflexibility to tolerate other realistic fault patterns. In this paper, we develop dynamic reconfiguration and incremental rerouting techniques that are fault specific. In this approach, the FPGA is initially routed without any extra interconnects for reconfiguration. When faults occur, the routed nets have to be minimally perturbed to allow these interconnects to be inserted “on-the-fly” for reconfiguration. These requirements are addressed in our minimally incremental rerouting technique Conv_T-DAG, which uses a cost-directed depth-first search strategy. We prove several results that establishes the near-optimality of Conv_T-DAG in terms of track overhead. To the best of our knowledge, this is the first time that an incremental rerouting technique has been developed for FPGAs. For several benchmark circuits, the static approach to tolerating one fault per row resulted in a 43% to 34% track overhead. Using the dynamic reconfiguration approach and Conv_T-DAG results in an average overhead of only 16%—an improvement of more than 50%. Over all circuits, the reconfiguration time per fault ranges from 16.8 to 72.9 secs. Simulation of smaller fault sets of one to four faults show very small track overheads ranging from 1.75% to 4.49%. Conv_T-DAG can also be used for interconnect fault tolerance.