Performance Penalty for Fault Tolerance in Roving STARs

Authors:
John M. Emmert;Charles E. Stroud;Jason A. Cheatham;Andrew M. Taylor;Pankaj Kataria;Miron Abramovici
Affiliations:
-;-;-;-;-;-
Venue:
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Year:
2000

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Abstract

In this paper we analyze the performance penalty of a fault-tolerant (FT) adaptive computing system (ACS) that implements the roving Self Testing AReas (STARs) approach for on-line testing and fault tolerance for FPGAs[1,5]. For most benchmarks, the presence of the STARs increases the critical path delay by 4.6% to 22%, and preallocating spare cells for fault tolerance causes an additional increase of up to 37%. We also present a procedure for estimating the worst case performance penalty caused by an incremental change of an already placed and routed FPGA. This estimate can be used to guide the selection of fault-tolerant reconfigurations to minimize their impact on the system timing. Our results show that the estimate is within 10% of the real delay values.