Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles
IEEE Transactions on Computers
Rectilinear shortest paths through polygonal obstacles in O(n(logn)2) time
SCG '87 Proceedings of the third annual symposium on Computational geometry
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
ISPD '98 Proceedings of the 1998 international symposium on Physical design
A channelless, multilayer router
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
DUNE: a multi-layer gridless routing system with wire planning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
An implicit connection graph maze routing algorithm for ECO routing
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Finding obstacle-avoiding shortest paths using implicit connection graphs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DUNE-a multilayer gridless routing system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Shortest path search using tiles and piecewise linear cost propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A metal-only-ECO solver for input-slew and output-loading violations
Proceedings of the 2009 international symposium on Physical design
Matching-based minimum-cost spare cell selection for design changes
Proceedings of the 46th Annual Design Automation Conference
Simultaneous functional and timing ECO
Proceedings of the 48th Design Automation Conference
| Hi-index | 0.00 |
Engineering Change Order (ECO) routing is frequently requested in the later design stage for the purpose of delay and noise optimization. ECO routing is complicated by huge existing obstacles and the requests for various design rules. Tile-based routers have work with fewer nodes of the routing graph than grid and connection-based routers; however, the number of nodes of the tile-based routing graph has grown to over a thousand millions for SOC designs. This work depicts a new ECO routing design flow with routing graph reduction and enhanced global routing flow. Routing graph reduction reduces the complexity of nodes by removing redundant tiles and aligning neighboring tiles to merge adjacent block tiles. Routing graph reduction reduces tile fragmentation such that the ECO router can run twice as fast without sacrificing routing quality. Enhanced global routing flow incorporates ECO global routing with extended routing and GCell restructuring to prevent routing failure in a routable routing. The ECO router with new design flow can perform up to 20 times faster than the original tile-based router, at the cost of only a very small decline in routing quality.