DUNE: a multi-layer gridless routing system with wire planning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A current driven routing and verification methodology for analog applications
Proceedings of the 37th Annual Design Automation Conference
An implicit connection graph maze routing algorithm for ECO routing
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Single step current driven routing of multiterminal signal nets for analog applications
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A minimum cost path search algorithm through tile obstacles
Proceedings of the 2001 international symposium on Physical design
Efficient minimum spanning tree construction without Delaunay triangulation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Cruise Missile Mission Planning: A Heuristic Algorithm for Automatic Path Generation
Journal of Heuristics
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Research directions for coevolution of rules and routers
Proceedings of the 2003 international symposium on Physical design
Routing using implicit connection graphs [VLSI design
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
An efficient tile-based ECO router with routing graph reduction and enhanced global routing flow
Proceedings of the 2005 international symposium on Physical design
An-OARSMan: obstacle-avoiding routing tree construction with good length performance
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the λ-geometry plane
Proceedings of the 2006 international symposium on Physical design
Proceedings of the 2006 international symposium on Physical design
Circuit-simulated obstacle-aware Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A full-scale solution to the rectilinear obstacle-avoiding Steiner problem
Integration, the VLSI Journal
Obstacle-avoiding rectilinear Steiner tree construction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree
Proceedings of the 2009 International Conference on Computer-Aided Design
Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach
Integration, the VLSI Journal
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We introduce a framework for a class of algorithms solving shortest path related problems, such as the one-to-one shortest path problem, the one-to-many shortest paths problem and the minimum spanning tree problem, in the presence of obstacles. For these algorithms, the search space is restricted to a sparse strong connection graph that is implicitly represented and its searched portion is constructed incrementally on-the-fly during search. The time and space requirements of these algorithms essentially depend on actual search behavior. Therefore, additional techniques or heuristics can be incorporated into search procedure to further improve the performance of the algorithms. These algorithms are suitable for large VLSI design applications with many obstacles