An efficient tile-based ECO router with routing graph reduction and enhanced global routing flow
Proceedings of the 2005 international symposium on Physical design
The oct-touched tile: a new architecture for shape-based routing
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Novel wire density driven full-chip routing for CMP variation control
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 international symposium on Physical design
A generalization of Dijkstra's shortest path algorithm with applications to VLSI routing
Journal of Discrete Algorithms
A novel wire-density-driven full-chip routing system for CMP variation control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Double patterning lithography aware gridless detailed routing with innovative conflict graph
Proceedings of the 47th Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integration, the VLSI Journal
RegularRoute: an efficient detailed router with regular routing patterns
Proceedings of the 2011 international symposium on Physical design
Redundant-wires-aware ECO timing and mask cost optimization
Proceedings of the International Conference on Computer-Aided Design
TRIAD: a triple patterning lithography aware detailed router
Proceedings of the International Conference on Computer-Aided Design
Stitch-aware routing for multiple e-beam lithography
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.03 |
Advances of very large scale integration technologies present two challenges for routing problems: (1) the higher integration of transistors due to shrinking of featuring size and (2) the requirement for off-grid routing due to the variable-width variable-spacing design rules imposed by optimization techniques. In this paper, we present a multilayer gridless detailed routing system for deep submicrometer physical designs. Our detailed routing system uses a hybrid approach consisting of two parts: (1) an efficient variable-width variable-spacing detailed routing engine and (2) a wire-planning algorithm providing high-level guidance as well as ripup and reroute capabilities. Our gridless routing engine is based on an efficient point-to-point gridless routing algorithm using an implicit representation of a nonuniform grid graph. We proved that such a graph guarantees a gridless connection of the minimum cost in multilayer variable-width and variable-spacing routing problem. A novel data structure using a two-level slit tree plus interval tree in combination of cache structure is developed to support efficient queries into the connection graph. Our experiments show that this data structure is very efficient in memory usage while very fast in answering maze expansion related queries. Our detailed routing system also features a coarse grid-based wire-planning algorithm that uses exact gridless design rules (variable-width and variable-spacing) to accurately estimate the routing resources and distribute nets into routing regions. The wire-planning method also enables efficient ripup and reroute in gridless routing. Unlike previous approaches for gridless routing that explore alternatives of blocked nets by gradually tightening the design rules, our planning-based approach can take the exact gridless rules and resolve the congestion and blockage at a higher level. Our experimental results show that using the wire-planning algorithm in our detailed routing system can improve the routability and also speed up the runtime by 3 to 17 times