Low power architecture of the soft-output Viterbi algorithm
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
FPGA implementation of Viterbi decoder
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
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When data is stored, compressed, or communicated through a media such as cable or air, sources of noise and other parameters such as EMI, crosstalk, and distance can considerably effect the reliability of these data. Orthogonal Code is one of the codes that can detect errors and correct corrupted data. In this paper we present a new methodology to enhance error detection capabilities of the orthogonal code. A new decoding technique called Viterbi decoder was used to speed up the process. The existing techniques are not able to achieve high efficiency and to meet bandwidth requirements, especially with the increase in the quantity of data transmitted. The technique was implemented experimentally using Field Programmable Gate Arrays (FPGA). The results shows the proposed technique improves the detection capabilities by increasing the speed twice, and corrects up to 3 bits of error.