Digital modulation and coding
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Unveiling turbo codes: some results on parallel concatenated coding schemes
IEEE Transactions on Information Theory
A distance spectrum interpretation of turbo codes
IEEE Transactions on Information Theory - Part 1
Error bounds for convolutional codes and an asymptotically optimum decoding algorithm
IEEE Transactions on Information Theory
Optimal decoding of linear codes for minimizing symbol error rate (Corresp.)
IEEE Transactions on Information Theory
Energy efficient data transfer and storage organization for a MAP turbo decoder module
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Memory Power Reduction for High-Speed Implementation of Turbo Codes
Journal of VLSI Signal Processing Systems
A low-power VLSI architecture for turbo decoding
Proceedings of the 2003 international symposium on Low power electronics and design
FPGA implementation of Viterbi decoder
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
FPGA implementation of Viterbi decoder
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Comparison of decoding algorithms for concatenated turbo codes
EHAC'05 Proceedings of the 4th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Traceback-Based Optimizations for Maximum a Posteriori Decoding Algorithms
Journal of Signal Processing Systems
Area-efficient high-throughput MAP decoder architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA based implementation of decoding architectures
Proceedings of the International Conference & Workshop on Emerging Trends in Technology
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An important technique for reducing pow er consumption in VLSI systems is strength reduction, the substitution of a less-costly operation such as a shift, for a more-costly operation such a multiplication. Using a logarithmic number represen tation provides sev eral opportunities for strength reductions; in particular, m ultiplicationis performed as the fixed-point addition of logarithms, and extracting a square root is implemented via a shift. These reductions occur transparently at the hardware level; consequently relativ ely little algorithmic modification is required, and they are readily applicable to adaptive filtering. For performing Givens rotations in the QR decomposition recursiv e least squares adaptive filter, logarithmic arithmetic is shown to compare favorably to other strength reduction techniques, such as CORDIC arithmetic, in terms of switched capacitance and numerical accuracy.