Low power architecture of the soft-output Viterbi algorithm
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Energy efficient data transfer and storage organization for a MAP turbo decoder module
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Design of low-power high-speed maximum a priori decoder architectures
Proceedings of the conference on Design, automation and test in Europe
Energy efficient turbo decoding for 3G mobile
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Low-power VLSI decoder architectures for LDPC codes
Proceedings of the 2002 international symposium on Low power electronics and design
Architectural strategies for low-power VLSI turbo decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI architectures for SISO-APP decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Area-efficient high-speed decoding schemes for turbo decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Journal on Selected Areas in Communications
Error-resilient low-power Viterbi decoders
Proceedings of the 13th international symposium on Low power electronics and design
Bit-level extrinsic information exchange method for double-binary turbo codes
IEEE Transactions on Circuits and Systems II: Express Briefs
Error-resilient low-power Viterbi decoder architectures
IEEE Transactions on Signal Processing
Design space exploration of the turbo decoding algorithm on GPUs
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
A WiMAX turbo decoder with tailbiting BIP architecture
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Flexible LDPC/Turbo Decoder Architecture
Journal of Signal Processing Systems
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Iterative decoders such as turbo decoders have become integral components of modern broadband communication systems because of their ability to provide substantial coding gains. A key computational kernel in iterative decoders is the maximum a posteriori probability (MAP) decoder. The MAP decoder is recursive and complex, which makes high-speed implementations extremely difficult to realize. In this paper, we present block-interleaved pipelining (BIP) as a new high-throughput technique for MAP decoders. An area-efficient symbol-based BIP MAP decoder architecture is proposed by combining BIP with the well-known look-ahead computation. These architectures are compared with conventional parallel architectures in terms of speed-up, memory and logic complexity, and area. Compared to the parallel architecture, the BIP architecture provides the same speed-up with a reduction in logic complexity by a factor of M, where M is the level of parallelism. The symbol-based architecture provides a speed-up in the range from 1 to 2 with a logic complexity that grows exponentially M with and a state metric storage requirement that is reduced by a factor M of as compared to a parallel architecture. The symbol-based BIP architecture provides speed-up in the range M to 2M with an exponentially higher logic complexity and a reduced memory complexity compared to a parallel architecture. These high-throughput architectures are synthesized in a 2.5-V 0.25-µm CMOS standard cell library and post-layout simulations are conducted. For turbo decoder applications, we find that the BIP architecture provides a throughput gain of 1.96 at the cost of 63% area overhead. For turbo equalizer applications, the symbol-based BIP architecture enables us to achieve a throughput gain of 1.79 with an area savings of 25%.