A WiMAX turbo decoder with tailbiting BIP architecture

Authors:
Hiroaki Arai;Naoto Miyamoto;Koji Kotani;Hisanori Fujisawa;Takashi Ito
Affiliations:
Tohoku University;Tohoku University;Tohoku University;Fujitsu Laboratories Ltd., Aoba-ku, Sendai, Japan;Tohoku University
Venue:
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Year:
2010

Citing 2
Cited 0

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Tailbiting MAP decoders

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Abstract

A tailbiting block-interleaved pipelining (TB-BIP) is proposed for deeply-pipelined turbo decoders. Conventional sliding window block-interleaved pipelining (SW-BIP) turbo decoders suffer from many warm-up calculations when the number of pipeline stages is increased. However, by using TB-BIP, more than 50% of the warm-up calculations are reduced as compared to SW-BIP. We have implemented a TB-BIP WiMAX turbo decoder with four pipeline stages in the area of 3.8 mm2 using a 0.18 μm CMOS technology. The chip achieved 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.