A Highly Efficient Domain-Programmable Parallel Architecture for Iterative LDPCC Decoding
ITCC '01 Proceedings of the International Conference on Information Technology: Coding and Computing
A low-power VLSI architecture for turbo decoding
Proceedings of the 2003 international symposium on Low power electronics and design
A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes
Journal of VLSI Signal Processing Systems
Multilevel LDPC codes design for multimedia communication CDMA system
EURASIP Journal on Wireless Communications and Networking - Special issue on innovative signal transmission and detection techniques for next generation cellular CDMA systems
Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
High-throughput decoder for low-density parity-check code
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Parallel turbo-sum-product decoder architecture for quasi-cyclic LDPC codes
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Power-efficient LDPC code decoder architecture
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Configurable LDPC Decoder Architectures for Regular and Irregular Codes
Journal of Signal Processing Systems
Optimal overlapped message passing decoding of quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Multiple-rate low-density parity-check codes with constant blocklength
IEEE Transactions on Communications
Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices
IEEE Transactions on Communications
Conflict resolution by matrix reordering for DVB-T2 LDPC decoders
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Constructing short-length irregular LDPC codes with low error floor
IEEE Transactions on Communications
An area-efficient and low-power multirate decoder for quasi-cyclic low-density parity-check codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Area-efficient high-throughput MAP decoder architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A memory efficient FPGA implementation of quasi-cyclic LDPC decoder
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and Finite Precision Optimization for Layered LDPC Decoders
Journal of Signal Processing Systems
Switching Activity Minimization in Iterative LDPC Decoders
Journal of Signal Processing Systems
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Iterative decoding of low-density parity check codes (LDPC) using the message-passing algorithm have proved to be extraordinarily effective compared to conventional maximum-likelihood decoding. However, the lack of any structural regularity in these essentially random codes is a major challenge for building a practical low-power LDPC decoder. In this paper, we jointly design the code and the decoder to induce the structural regularity needed for a reduced complexity parallel decoder architecture. This interconnect-driven code design approach eliminates the need for a complex interconnection network while still retaining the algorithmic performance promised by random codes. Moreover, we propose a new approach for computing reliability metrics based on the BCJR algorithm that reduces the message switching activity in the decoder compared to existing approaches. Simulations show that the proposed approach results in power savings of up to 85.64% over conventional implementations.