Low-power VLSI decoder architectures for LDPC codes
Proceedings of the 2002 international symposium on Low power electronics and design
A Scalable Architecture for LDPC Decoding
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
Fast convergence algorithm for decoding of low density parity check codes
WSEAS TRANSACTIONS on COMMUNICATIONS
New code construction method and high-speed VLSI codec architecture for repeat-accumulate codes
WSEAS TRANSACTIONS on COMMUNICATIONS
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Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. The decoder implementation complexity has been the bottleneck of its application. This paper presents an implementation of Quasi-Cyclic Low-Density Parity-Check decoder by using FPGA. Modified Min-Sum decoding algorithm is applied to reduce the memory size needed for information storage. Partially parallel structures, memory management and pipelining schemes are discussed in this paper.