Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
High-throughput decoder for low-density parity-check code
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A memory efficient partially parallel decoder architecture for quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Configurable LDPC Decoder Architectures for Regular and Irregular Codes
Journal of Signal Processing Systems
Low-complexity high-speed decoder design for quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance enhancement of IEEE 802.11n wireless LAN using irregular LDPCC
WOCN'09 Proceedings of the Sixth international conference on Wireless and Optical Communications Networks
Performance evaluation and ASIC design of LDPC decoder for IEEE 802.11n
CCNC'09 Proceedings of the 6th IEEE Conference on Consumer Communications and Networking Conference
RTL design of LDPC decoder for IEEE802.11n WLAN
ISCIT'09 Proceedings of the 9th international conference on Communications and information technologies
On the usage of projective geometry based LDPC codes for wireless applications
ICICS'09 Proceedings of the 7th international conference on Information, communications and signal processing
A generic scalable architecture for min-sum/offset-min-sum unit for irregular/regular LDPC decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An area-efficient and low-power multirate decoder for quasi-cyclic low-density parity-check codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A memory efficient FPGA implementation of quasi-cyclic LDPC decoder
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
Data Parallel Implementation of Belief Propagation in Factor Graphs on Multi-core Platforms
International Journal of Parallel Programming
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This paper presents a semi-parallel architecture for decodingLow Density Parity Check (LDPC) codes. A modifiedversion of Min-Sum algorithm has been used which hasthe advantage of simpler computations compared to Sum-Productalgorithm without any loss in performance. Specialstructure of the parity check matrix of the proposed codeleads to an efficient semi-parallel implementation of the decoderfor a family of (3, 6) LDPC codes.A prototype architecturehas been implemented in VHDL on programmablehardware. The design is easily scalable and reconfigurablefor larger block sizes. Simulation results show that our proposeddecoder for a block length of 1536 bits can achievedata rates up to 127 Mbps.