Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
A Synthesizable IP Core for DVB-S2 LDPC Code Decoding
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Joint (3,k)-regular LDPC code and decoder/encoder design
IEEE Transactions on Signal Processing
Quasicyclic low-density parity-check codes from circulant permutation matrices
IEEE Transactions on Information Theory
An area-efficient and low-power multirate decoder for quasi-cyclic low-density parity-check codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A memory efficient parallel layered QC-LDPC decoder for CMMB systems
Integration, the VLSI Journal
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This paper presents a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check (QC-LDPC) codes using (modified) min-sum algorithm for decoding. In general, over 30% of memory can be saved over conventional partially parallel decoder architectures. Efficient techniques have been developed to reduce the computation delay of the node processing units and to minimize hardware overhead for parallel processing. The proposed decoder architecture can linearly increase the decoding throughput with a small percentage of extra hardware. Consequently, it facilitates the applications of LDPC codes in area/power sensitive high-speed communication systems.