High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems
Journal of VLSI Signal Processing Systems
A memory efficient partially parallel decoder architecture for quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Massive parallel LDPC decoding on GPU
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
A scalable LDPC decoder ASIC architecture with bit-serial message exchange
Integration, the VLSI Journal
Optimal overlapped message passing decoding of quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel LDPC Decoding on the Cell/B.E. Processor
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
How GPUs can outperform ASICs for fast LDPC decoding
Proceedings of the 23rd international conference on Supercomputing
Low Complexity Decoder Architecture for Low-Density Parity-Check Codes
Journal of Signal Processing Systems
A low-complexity hybrid LDPC code encoder for IEEE 802.3an (10GBase-T) ethernet
IEEE Transactions on Signal Processing
Parallel LDPC decoding on GPUs using a stream-based computing approach
Journal of Computer Science and Technology - Special section on trust and reputation management in future computing systmes and applications
Impact of Approximation Error on the Decisions of LDPC Decoding
Journal of Signal Processing Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
| Hi-index | 35.69 |
Recently, low-density parity-check (LDPC) codes have attracted a lot of attention in the coding theory community. However, their real-world applications are still problematic mainly due to the lack of effective decoder/encoder hardware design approaches. In this paper, we present a joint (3,k)-regular LDPC code and decoder/encoder design technique to construct a class of (3,k)-regular LDPC codes that not only have very good error-correcting capability but also exactly fit to high-speed partly parallel decoder and low-complexity encoder implementations. We also develop two techniques to further modify this joint design scheme to achieve more flexible tradeoffs between decoder hardware complexity and decoding speed.