Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
A Flexible Hardware Encoder for Low-Density Parity-Check Codes
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Joint (3,k)-regular LDPC code and decoder/encoder design
IEEE Transactions on Signal Processing
Efficient encoding of low-density parity-check codes
IEEE Transactions on Information Theory
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This paper presents a novel hybrid encoding method for encoding of low-density parity-check (LDPC) codes. The design approach is applied to design 10-Gigabit Ethernet transceivers over copper cables. For a specified encoding speed, the proposed method requires substantially lower complexity in terms of area and storage. Furthermore, this method is generic and can be adapted easily for other LDPC codes. One major advantage of this design is that it does not require column swapping and it maintains compatibility with optimized LDPC decoders. For a 10-Gigabit Ethernet transceiver which is compliant with the IEEE 802.3an standard, the proposed sequential (5-Parallel) hybrid architecture has the following implementation properties: critical path: (log2(324) + 1)Txor + Tand, number of XOR gates: 11 056, number of AND gates: 1620, and ROM storage: 104 976 bits (which can be minimized to 52 488 bits using additional hardware). This method achieves comparable critical path, and requires 74% gate area, 10% ROM storage as compared with a similar 10-Gigabit sequential (5-Parallel) LDPC encoder design using only the G matrix multiplication method. Additionally the proposed method accesses fewer bits per cycle than the G matrix method which reduces power consumption by about 82%.