A Flexible Hardware Encoder for Low-Density Parity-Check Codes

Authors:
Dong-U Lee;Wayne Luk;Connie Wang;Christopher Jones;Michael Smith;John Villasenor
Affiliations:
Imperial College, London, UK;Imperial College, London, UK;University of California, Los Angeles, USA;University of California, Los Angeles, USA;University of California, Los Angeles, USA;University of California, Los Angeles, USA
Venue:
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2004

Citing 0
Cited 5

A Gaussian Noise Generator for Hardware-Based Simulations

IEEE Transactions on Computers
Pipelined implementation of a real time programmable encoder for low density parity check code on a reconfigurable instruction cell architecture

Proceedings of the conference on Design, automation and test in Europe
Low-complexity high-speed decoder design for quasi-cyclic LDPC codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-complexity hybrid LDPC code encoder for IEEE 802.3an (10GBase-T) ethernet

IEEE Transactions on Signal Processing
Selective secure error correction on SPIHT coefficients for pervasive wireless visual network

International Journal of Ad Hoc and Ubiquitous Computing

Quantified Score

Hi-index	0.01

Visualization

Abstract

We describe a flexible hardware encoder for regular and irregular low-density parity-check (LDPC) codes. Although LDPC codes achieve achieve better performance and lower decoding complexity than Turbo codes, a major drawback of LDPC codes is their apparently high encoding complexity. Using an efficient encoding method proposed by Richardson and Urbanke, we present a hardware LDPC encoder with linear encoding complexity. The encoder is flexible, supporting arbitrary H matrices, rates and block lengths. An implementation for a rate 1/2 irregular length 2000 LDPC code encoder on a Xilinx Virtex-II XC2V4000-6 FPGA takes up 4% of the device.It runs at 143MHz and has a throughput of 45 million codeword bits per second (or 22 million information bits per second) with a latency of 0.18ms. The performance can be improved by exploiting parallelism: several instances of the encoder can be mapped onto the same chip to encode multiple message blocks concurrently. An implementation of 16 instances of the encoder on the same device at 82MHz is capable of 410 million codeword bits per second, 80 times faster than an Intel Pentium-IV 2.4GHz PC.