Good Codes Based on Very Sparse Matrices
Proceedings of the 5th IMA Conference on Cryptography and Coding
A Flexible Hardware Encoder for Low-Density Parity-Check Codes
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
System-level scheduling on instruction cell based reconfigurable systems
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A linear time erasure-resilient code with nearly optimal recovery
IEEE Transactions on Information Theory - Part 1
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
A compact 1.1-Gb/s encoder and a memory-based 600-Mb/s decoder for LDPC convolutional codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
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This paper presents pipelined implementation of a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for frame sizes from 576 to 2304 and for five different code rates. H matrix is efficiently generated and stored for a particular frame size and code rate. The encoder is implemented on Reconfigurable Instruction Cell Architecture which has recently emerged as an ultra low power, high performance, ANSI-C programmable embedded core. Different general and architecture specific optimization techniques are applied to enhance the throughput. With the architecture, a throughput from 10 to 19 Mbps has been achieved. The maximum throughput achieved with pipelining/ multi-core is 78 Mbps.